What is an Assertion?
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.
When the user listens to assertion first green and red arrows come in the mind.
Assertions, also known as a checkers.
USER WANTS CODE:
module basic_assertion();
bit a,b,clk;
always #5 clk =~ clk;
always @(posedge clk)
begin
assert (a && b)
begin
$display("A && B assertion PASS");
end
else
begin
$display("A && B assertion FAIL");
end
assert(a || b)
begin
$display("A || B assertion Pass");
end
else
begin
$display("A || B assertion FAIL");
end
assert(!a)
begin
$display("!A assertion FAIL");
end
else
begin
$display("!A assertion FAIL");
end
end
initial
begin
clk = 0;
a = 0;
b = 0;
#5;
a = 1;
b = 1;
#15;
a = 0;
b = 0;
#15;
a = 1;
end
initial
begin
#100;
$finish;
end
endmodule
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.
When the user listens to assertion first green and red arrows come in the mind.
Assertions, also known as a checkers.
Why is an assertion required?
- Provide the protocol check and functional check.
- Supports Multi-Clock Domain Crossing.
- Provide good control to Enable/Disable the assertion.
Application:
- Scenario 1: Signals 'a' and 'b' always should be sync.
- Supports Multi-Clock Domain Crossing.
- Provide good control to Enable/Disable the assertion.
Application:
- Scenario 1: Signals 'a' and 'b' always should be sync.
- Scenario 2: Either signal 'a' or 'b' should be high.
- Scenario 3: Signal 'a' should not go high.
- Scenario 3: Signal 'a' should not go high.
USER WANTS CODE:
module basic_assertion();
bit a,b,clk;
always #5 clk =~ clk;
always @(posedge clk)
begin
assert (a && b)
begin
$display("A && B assertion PASS");
end
else
begin
$display("A && B assertion FAIL");
end
assert(a || b)
begin
$display("A || B assertion Pass");
end
else
begin
$display("A || B assertion FAIL");
end
assert(!a)
begin
$display("!A assertion FAIL");
end
else
begin
$display("!A assertion FAIL");
end
end
initial
begin
clk = 0;
a = 0;
b = 0;
#5;
a = 1;
b = 1;
#15;
a = 0;
b = 0;
#15;
a = 1;
end
initial
begin
#100;
$finish;
end
endmodule
To run simulation click on below link:
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