Event control in Verilog

Requirement::
- Synchronization and Communication mechanism are essential to control the interaction between two processes.

Application:
- Last packet received, trigger the event to check update of status register value.
- Specific type packet received repeatedly based on that sample value for coverage.

Analogy:
- Traffic signal is the best example to explain event. Multiple vehicles are moving on the road. Now, to avoid accident traffic management system is required. So, need to block one root of the vehicles for certain time period. And later unblock the same and block the another root. Consider the traffic signal that block the vehicles for certain period of time. When timer is completed, signal will Unblock the vehicles.








USER WANT CODE:

module traffic_system;
event green_light; // to activate green light
initial
begin
  #20; // block the traffic
  ->green_light; // trigger event
  #10; // Unblock traffic
  $display(" green_light is asserted at %t ",$time);
end

always
begin
  #10;
  if(green_light.triggered) // check traffic status
    $display(" green_light is activated at %t",$time);
  else
    $display(" green_light is Not activated at %t",$time);
end

initial
#100 $finish;

endmodule


To run simulation click on below link:
Link: https://www.edaplayground.com/x/4Hny