Difference between task and function

To reuse the same lines of code again and again methods are used. System Verilog supports two types of methods.
(1) Function
(2) Task

Function:
- Delayed can NOT use in the function.
- Task WITHOUT delay can call in the function. It shouts only WARNING, not an ERROR.
- The function calls another function.
- The function can return value.

Task:
- Delayed can be inserted in the task.
- The task with DELAY can be called in the task.
- The function also can call in the task.
- The task can NOT return value.

The user can NOT call a task in function. Is it true? Is it shouts an ERROR?
NOT ALWAYS. The user can call a task in function if the definition of a task should NOT contain delay.

WITHOUT delay Warning: "warning-[teif] Task enabled inside a function"

WITH delay Error: "Function "function_name" has illegal use of delay or synchronization"


USER WANT CODE:

function hello();

  $display("This is Hello function");

  Hi(); // CALL TASK(without delay) INSIDE FUNCTION

endfunction

task Hi();

  //#1;  // without delay

  $display("This is Hi task");

  hello();

endtask

module top();

initial

   begin

     hello(); // Call function

     //Hi(); // call task

   end

endmodule

To run simulation click on below link:
Link: https://www.edaplayground.com/x/2uZ8

Basics of Assertions

What is an Assertion?
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.
When the user listens to assertion first green and red arrows come in the mind.
Assertions, also known as a checkers.

Why is an assertion required?

- Provide the protocol check and functional check.
- Supports Multi-Clock Domain Crossing.
- Provide good control to Enable/Disable the assertion.

Application:
- Scenario 1: Signals 'a' and 'b' always should be sync.

- Scenario 2: Either signal 'a' or 'b' should be high.
- Scenario 3: Signal 'a' should not go high.

USER WANTS CODE:

module basic_assertion();
  bit a,b,clk;
  always #5 clk =~ clk;

  always @(posedge clk)
  begin
  assert (a && b)
  begin
    $display("A && B assertion PASS");
  end
  else
  begin
    $display("A && B assertion FAIL");
  end
  assert(a || b)
  begin
    $display("A || B assertion Pass");
  end
  else
  begin
    $display("A || B assertion FAIL");
  end
  assert(!a)
  begin
    $display("!A assertion FAIL");    
  end
  else
  begin
    $display("!A assertion FAIL");
  end
  end
  initial
  begin
    clk = 0;
    a = 0;
    b = 0;
    #5;
    a = 1;
    b = 1;
    #15;
    a = 0;
    b = 0;
    #15;
    a = 1;
  end
  initial
  begin
    #100;
    $finish;    
  end

endmodule

To run simulation click on below link:

Link: https://www.edaplayground.com/x/3MUW