System Verilog provides the facility to execute an event in a specific order.
Application: In a pipeline structure, the user will receive requests in sequences. Now, according to the priority mechanism, execute the different process.
Example: Consider the entire packet frame structure. Design is producing frame structure with help of SOP(Start Of Packet), SOM(Start Of Message), EOM(End of Message) and EOP(End Of Packet) signal. The packet should follow the following order.
(1) SOP
(2) SOM
(3) EOM
(4) EOP
Irrespective of repetition of the same signal. All signals should assert to complete the entire frame.
USER WANT CODE:
module complete_frame;
event sop, som, eom, eop, start; // event name
initial
begin
#20; // Activate exect pin
-> start; // trigger event
#10 -> sop; // start of packet so, assert event sop.
#10 -> som; // start of message so, assert event som.
#10 -> eom; // end of message so, assert event eom.
#10 -> som; // start of message so, assert event som IGNORE
#10 -> eom; // end of message so, assert event eom.
#10 -> eop; // end of packet so, assert event eop.
end
always
begin
#10;
if(start.triggered) // check traffic status
begin
$display(" Execute pin is activated at %t",$time);
wait_order(sop, som, eom, eop) // IMPORTANT: ALL EVENTS SHOULD assert.
$display("\n Frame is completed function is WORKING at %0t",$time);
else
$error("Frame is NOT completed function is NOT WORKING at %0t",$time);
end
else
$display(" Execute pin is Not activated at %t",$time);
end
initial
#100 $finish;
