Verilog event limitation:
- Verilog event is static object.
- Reclaiming and event comparison of event is not possible.
- Pre-define option to execute event in specific order.
- Non-blocking event not supported.
- Level trigger option is not present.
System verilog enhance event type of VERILOG. All the above limitations are overcome by systemverilog event.
- Event comparison.
- Reclaiming event/Deactivate event.
- In SV event variable can assign another event variable or NULL.
Few scenarios:
(1) Event variable assigns to another event variable, both event variables refer the same synchronization object.
(2) Event variable assign to null, event variable is broken.
- An event can pass in an argument in a task.
(3) Event variable compare with another event or check existence of event.
System verilog event advantages are justified in an example.
USER WANT CODE:
module main;
event e1,e2,e3; // event declaration
initial begin
repeat(5)
begin
#10;
->e1; // trigger event
#5; // do some operation
e1 = e2; // assiging one event to another
#5;
e3 = null; // Deactivate event
end
end
initial
begin
repeat(4)
begin
#5 if(e1.triggered) // waiting to trigger event
$display("@%0t e1 event is triggered",$realtime);
else
$display("@%0t e1 event is not triggered",$realtime);
if(e1 == e2) // EVENT COMPARISON
$display("Event e1 and e2 are same event");
else
$display("Both events e1,e2 are NOT same event");
if(e3 == null)
$display("e3 is NULL event");
end
end
initial
#100 $finish;
endmodule
To run simulation click on below link:
Link: https://www.edaplayground.com/x/3cnU
